Analog IC Design of Min-Sum LDPC Decoder with the Stopping Iteration
碩士 === 國立臺北科技大學 === 電腦與通訊研究所 === 99 === The stopping iteration method is wildly used in digital decoder design; however, there are few analog decoders employ this method. Hence, we propose an analog min-sum decoder with stopping iteration method that has advantages on throughput, decoding performa...
Main Authors: | Sheng-Sung Chiu, 邱勝頌 |
---|---|
Other Authors: | 李文達 |
Format: | Others |
Language: | zh-TW |
Published: |
2011
|
Online Access: | http://ndltd.ncl.edu.tw/handle/v68u9t |
Similar Items
-
Chip Design of Analog Min-Sum LDPC Decoder Employing Adaptive Early Stop Iteration
by: Chia-Chan Chang, et al. -
IC Design of an Analog Min-Sum LDPC Decoder Employing New Current Mirror
by: Yun-Ho Chiu, et al. -
Analog IC Design of Normalized Log Sum-Product LDPC Decoder with the Stopping Iteration Method
by: Cheng-Hao Tsai, et al.
Published: (2013) -
Analog IC Design of Modified Offset Min-Sum LDPC Decoder
by: Jhih-Peng Lu, et al.
Published: (2014) -
IC Design of Analog Min-Sum Iterative Decoder
by: Chi-Wei Chang, et al.
Published: (2010)