High PSRR, Fast Transient Response LDO Design
碩士 === 國立中正大學 === 電機工程研究所 === 100 === This thesis presents an integrated Low Dropout (LDO) voltage regulator design which is suitable for low-voltage, low-power and high-performance system on a chip (SOC) application. Using the 1-V TSMC 90nm CMOS process, the proposed LDO voltage regulator can conve...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/37072577581274546777 |