High PSRR, Fast Transient Response LDO Design
碩士 === 國立中正大學 === 電機工程研究所 === 100 === This thesis presents an integrated Low Dropout (LDO) voltage regulator design which is suitable for low-voltage, low-power and high-performance system on a chip (SOC) application. Using the 1-V TSMC 90nm CMOS process, the proposed LDO voltage regulator can conve...
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ndltd-TW-100CCU004420202015-10-13T20:51:34Z http://ndltd.ncl.edu.tw/handle/37072577581274546777 High PSRR, Fast Transient Response LDO Design 高供應電源拒斥比、高速暫態反應之低壓降線性穩壓器設計 Chih-Ming Liao 廖志明 碩士 國立中正大學 電機工程研究所 100 This thesis presents an integrated Low Dropout (LDO) voltage regulator design which is suitable for low-voltage, low-power and high-performance system on a chip (SOC) application. Using the 1-V TSMC 90nm CMOS process, the proposed LDO voltage regulator can convert an input voltage of 1V to an output voltage of 0.85V-0.5V by adjusting the resistance of feedback network. With the requirement of power supply quality in low-voltage system, the proposed LDO voltage regulator have to achieve high Power Supply Rejection Ratio (PSRR) and fast transient response. First power noise isolation and ripple cancellation techniques are proposed to improve the PSRR of LDO voltage regulator effectively. Furthermore, a slew-rate enhancement circuit is applied to enhance the transient response. Simulation results show that at least -50dB PSRR is achieved at 0-1MHz for a load range of 0-100mA, while the output voltage variation is less than ± 3% of output voltage to ensure the power supply quality and performance of the load circuit. The current efficiency of the proposed LDO voltage regulator is 99.91%. Chung-Hsun Huang 黃崇勛 2012 學位論文 ; thesis 77 zh-TW |
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碩士 === 國立中正大學 === 電機工程研究所 === 100 === This thesis presents an integrated Low Dropout (LDO) voltage regulator design which is suitable for low-voltage, low-power and high-performance system on a chip (SOC) application. Using the 1-V TSMC 90nm CMOS process, the proposed LDO voltage regulator can convert an input voltage of 1V to an output voltage of 0.85V-0.5V by adjusting the resistance of feedback network. With the requirement of power supply quality in low-voltage system, the proposed LDO voltage regulator have to achieve high Power Supply Rejection Ratio (PSRR) and fast transient response. First power noise isolation and ripple cancellation techniques are proposed to improve the PSRR of LDO voltage regulator effectively. Furthermore, a slew-rate enhancement circuit is applied to enhance the transient response. Simulation results show that at least -50dB PSRR is achieved at 0-1MHz for a load range of 0-100mA, while the output voltage variation is less than ± 3% of output voltage to ensure the power supply quality and performance of the load circuit. The current efficiency of the proposed LDO voltage regulator is 99.91%.
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Chung-Hsun Huang |
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Chung-Hsun Huang Chih-Ming Liao 廖志明 |
author |
Chih-Ming Liao 廖志明 |
spellingShingle |
Chih-Ming Liao 廖志明 High PSRR, Fast Transient Response LDO Design |
author_sort |
Chih-Ming Liao |
title |
High PSRR, Fast Transient Response LDO Design |
title_short |
High PSRR, Fast Transient Response LDO Design |
title_full |
High PSRR, Fast Transient Response LDO Design |
title_fullStr |
High PSRR, Fast Transient Response LDO Design |
title_full_unstemmed |
High PSRR, Fast Transient Response LDO Design |
title_sort |
high psrr, fast transient response ldo design |
publishDate |
2012 |
url |
http://ndltd.ncl.edu.tw/handle/37072577581274546777 |
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