Optimization for Clock Network with Clock-Gating Cells and Multi-Bit Flip-Flops
碩士 === 國立中正大學 === 電機工程研究所 === 100 === Low power technology is an important issue in modern circuit design, several techniques are proposed to optimize power consumption recently. Applying multi-bit flip-flops (MBFFs) and clock gates (CGs) are two of the most effective techniques to save power consum...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/35834063322957013952 |