| Summary: | 碩士 === 國立中正大學 === 電機工程研究所 === 100 === Low power technology is an important issue in modern circuit design, several techniques are proposed to optimize power consumption recently. Applying multi-bit flip-flops (MBFFs) and clock gates (CGs) are two of the most effective techniques to save power consumption of clock network. In this thesis, we present a novel approach to optimize clock network power with clock gates and multi-bit flip-flops while considering the placement density constraints, timing slack constraints and setup time constraint. Experimental results show that our algorithms are very effective in reducing clock dynamic power consumption, clock net wirelength, buer number and improve setup time violation of multi-bit flip-flops and clock gates circuit.
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