Spur reduction in PLL by phase error calibration
碩士 === 長庚大學 === 電機工程學系 === 100 === Use signal synchronization is importance in phase-locked loop (PLL) but the conventional CMOS charge-pump circuits have some current mismatch problems. The reference signal and fed back signal induces a phase error which deteriorates the performance of the phase-lo...
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| Format: | Others |
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2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/24289009474407560833 |