A low phase noise PLL using novel band-selection VCO
碩士 === 中原大學 === 電子工程研究所 === 100 === PLL (Phase lock loop) has become a very important IP (Intellectual Property) for SOC (system on a chip), such as oscillator in the radio frequency circuit and the high speed I/O or in the power management IC. In this project, we designed a novel PLL which can sele...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/70146944232478338261 |