Simultaneously Considering Layout Area and TSV Wire Length on TSV Placement for 3D IC
碩士 === 大葉大學 === 資訊工程學系碩士班 === 100 === The semiconductor industry into the 3D IC technology and Through Silicon Vias (TSV) technology become increasingly important. On the same circuit design, 3D IC achieves high density, low power consumption and good timing slack. Chemical-Mechanical Polishing (CMP...
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| Format: | Others |
| Language: | zh-TW |
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2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/02402975749474909319 |