A Low Power Cache Coherence Protocol Design for Multiprocessors
碩士 === 逢甲大學 === 資訊工程所 === 100 === It’s a common situation that users run multiple tasks at the same time nowadays and it becomes more and more popular to utilize multiprocessors to deal with this situation. To reduce memory access latency, we usually add a high-speed cache between CPU and memory. An...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2012
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/86703307255327568772 |