VLSI Design And Implementation Of An All Digital Duty Cycle Corrector
碩士 === 國立金門大學 === 電資研究所 === 100 === Phase-Locked Loop (PLL) and Delay-Locked Loop (DLL) were widely used in communication systems, especially for the circuit design of high-speed communication and SOC (System on a Chip). The PLL or DLL circuits have the functions of clock deskew, clock recovery and...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2011
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/02309853494120625963 |