Design of 1.25 to 2.5 Gb/s Clock and Data Recovery Circuits
碩士 === 國立高雄應用科技大學 === 電子工程系 === 100 === The noise appears on the data after the data are transmitted from a transmitter to a receiver through an optical fiber. At an optical receiver, the clock and data recovery (CDR) circuit can generate a low jitter clock and recover low distortion data. In this t...
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| Format: | Others |
| Language: | zh-TW |
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| Online Access: | http://ndltd.ncl.edu.tw/handle/47762076950778090221 |