Design of a Clock-Deskew Buffer Circuit for Chip-to-Chip Links
碩士 === 國立中興大學 === 電機工程學系所 === 100 === With the rapid advances in CMOS technology, the demand for highly integrated VLSI circuit has grown exponentially in recent years. As the system frequency is rising, the problem of timing jitter for circuit modules is more serious. It will decrease the speed...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/06259505785414270515 |