A Successive Approximation ADC with Resistor-Capacitor Hybrid Structure
碩士 === 國立成功大學 === 電機工程學系碩博士班 === 100 === This thesis presents a 10-bit 50MS/S successive approximation ADC with low input capacitance that uses an on-chip resistive ladder and capacitor array to arrange a new switching scheme. This analog to digital converter possesses a predictive circuit in orde...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2012
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/12587977983657161660 |