A 10-Bit Area-Efficient SAR ADC
碩士 === 國立暨南國際大學 === 電機工程學系 === 100 === In this paper, an area-efficient successive approximation register (SAR) analog-to-digital converter (ADC) with a dithering Vref is proposed. It reuses the capacitive array with the reconfiguration of Vref to Vref±ΔV for reducing dramatically the ADC’s area. Th...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/69383844125227169450 |