A 10-Bit Area-Efficient SAR ADC

• Main Authors: Chao,Hao-tsun, 趙浩淳
• Other Authors: Lu,Chih-wen
• Format: Others
• Language: zh-TW
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/69383844125227169450

碩士 === 國立暨南國際大學 === 電機工程學系 === 100 === In this paper, an area-efficient successive approximation register (SAR) analog-to-digital converter (ADC) with a dithering Vref is proposed. It reuses the capacitive array with the reconfiguration of Vref to Vref±ΔV for reducing dramatically the ADC’s area. The 2N resolution is achieved by the N bit SAR ADC. In order to resolve the kickback noise, a cascode common gate amplifier is used in the comparator. To verify the proposed scheme, the proposed SAR ADC is implemented in a TSMC 0.18 μm 1P6M CMOS process with a supply voltage of 1.8V. The simulation results show that the capacitor area is reduced by 96% compared with the conventional 10-bit SAR-ADC. The ADC simulation achieves a SNDR of 60.6dB and ENOB of 9.767 bit when operating at 14MS/s. The measured SNDR is 29.79dB, the ENOB is 4.66.