Design And Implementation Of 19-29 GHz CMOS Receiver Front-End And A 8 Bit Analog-To-Digital Converter

• Main Authors: Chen, WeiJen, 陳威仁
• Other Authors: Lin, YoSheng
• Format: Others
• Language: en_US
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/80374876586748373284

碩士 === 國立暨南國際大學 === 電機工程學系 === 100 === In this thesis, we using CMOS process to implement receiver front-end circuit, and divided into two part: a 19~29GHz Low Noise Amplifier applied to receiver system and an 8-bit Analog-to-Digital Converter simulation and implement. The first part is a 19~29GHz Low Noise Amplifier applied to receiver system, and we use 0.18μm CMOS technology provided by TSMC. In this study, the first stage circuit uses the Common Source amplifier structure, which aims to provide low-frequency gain and broadband matching network. Appropriate choice of the transistor and transmission line will adjust its gain flatness and S11 match, and also have a great relationship with the level of noise. The characteristics of this LNA is the second stage, we using a cascode structure and joined a inductor L4 between M2 and M3, because of Cascode itself parasitic capacitance will affect the circuit characteristics, as well as insufficient bandwidth so we use L4 to resonance stray capacitance, it could improve gain and flatness. Measurement results: at 19 ~ 29GHz S11 is -5 ~-16dB, S22 are less than -7 and the gain is 8.63 ± 0.21dB, reason for S11 higher than -10 is the transmission at the input had not matching well; this circuit power consumption is 8.49mW. The second part is an 8-bit analog to digital converter, this circuit is also using 0.18μm CMOS process technology provided by TSMC. The ADC is designed for an 8 bit output, dual time clock input, the sinusoidal signal from sample and hold input and maintaining for system working is controlled from SAR reset clock, the shift-generator produce a series clock to control sampling time and hold signal time, the comparator is differential input, signal is from sample and hold output and DAC output. Clock control from four flip-flop circuit and in addition to 16 clocks, a single flip-flop circuits as an addition to the two so the 4 cascaded to form in addition to the 2, 4, 8, 16, at last we using a AND gate to produce a 16 clock of a period; Dac is the traditional architecture of the capacitor array, in this particular switch array using the inverter instead of the traditional transmission gate, this approach benefit is based on the capacitor size to determine the charge rate, This is because in same voltage, the charging speed of the large capacitor must be slower than small capacitor, and these inaccuracy may cause SAR or comparator matching error to cause INL/DNL, so the large capacitor we could use the number of multi-inverter parallel to increasing charge time, and using less number of multi-inverter parallel to decrease charge time, to make the same time between large and small capacitor charge time. The SAR A/D Converter architecture is constitute by sample and hold circuit, comparator circuit, the buffer and maintain output circuit, the clock control circuit, the logic control circuits, digital-to-analog converter circuit, this 8-bit A/D Converter input signal of 3kHz clock is 1MHz.