Performance-Driven Obstacle-Avoiding Routing Tree with Fixed Buffers
碩士 === 國立交通大學 === 資訊科學與工程研究所 === 100 === With the rapid evolution of manufacturing technology, interconnect delay has more impact than gate delay on chip performance. To design a good routing tree topology considering fixed buffers is important to improve timing. This paper focus on how to use pre-d...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2011
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/47555939767923816858 |