| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 100 === Electrostatic discharge (ESD) is the main reason that causes electrical overstress (EOS) on microelectronic products. Recently, as technology scaling down to the deep sub-micron, more integrated circuits are integrated into single chip to decrease the cost of microelectronic products. Due to thinner oxide and shallower junction depth in advance technology, microelectronic products equipped with CMOS ICs are more susceptible to ESD damage. Therefore, ESD protection has become an important reliability issue in CMOS ICs.
System-level ESD tests is an increasingly important reliability issue for CMOS ICs. It has been reported that reliability issues still exist in CMOS ICs under system-level ESD tests, even though they have passed component-level ESD specifications. The transient noise generated by system-level ESD events can cause microelectronic system into locked state, frozen state, or even hardware damage such as transient-induced latch-up. For traditional solutions, extra discrete components are often added on printed circuit board (PCB) to suppress system-level ESD events in microelectronic products. However, those discrete components are substantially increasing the cost of microelectronic products. As a result, chip-level solutions with silicon integration and to meet high system-level ESD specification for microelectronic products are strongly requested by IC industry.
In this thesis, first, with silicon controlled rectifier (SCR) device as memory unit, on-chip SCR-based transient detection circuit has been proposed and fabricated in 180nm CMOS process. It has been investigated that, under system-level ESD tests, the SCR device can be triggered on and the cross voltage can be dropped into holding voltage. Experimental results has confirmed that, when system-level ESD events happens, the detection circuit can successfully detect and memorize the occurrence of positive and negative fast electrical transients coupled on the power line and ground line of CMOS ICs. Furthermore, with hardware/firmware system co-design, display panel can automatically recover from the frozen state into normal operation after the system-level ESD zapping.
Second, a new on-chip transient-to-digital converter composed of four CR-based transient detection circuits and four different noise filters has been successfully designed and verified in a 130nm CMOS process with 1.8-V devices. By using the current amplification techniques, capacitor used in the noise filter could be reduced to save silicon area and avoid leakage in deep submicron process. The output digital codes of the proposed on-chip transient-to-digital converter correspond to different level of positive/negative ESD voltages under system-level ESD tests. And these digital codes can be used as the firmware index to execute partial/total auto-recovery procedures in microelectronic systems.
This thesis is divided into five parts. In the first chapter, international standards about system-level ESD are generally guided. In chapter two, some traditional solutions to overcome system-level ESD events are collected and introduced. In chapter three, on-chip SCR-based transient detection circuit is proposed. In chapter four, on-chip transient-to-digital converter has been simulated in detail and circuit performance has been verified under system-level ESD tests. The last chapter includes conclusions and future works.
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