Study on the CNT-first-approach Technology of Carbon Nanotube-based Through Silicon Vias with Co-deposited Catalytic Metals for Three Dimensional Integrated Circuits

• Main Authors: Chiang, Chun-Hsien, 江俊賢
• Other Authors: Cheng, Yu-Ting
• Format: Others
• Language: en_US
• Published: 2011
• Online Access: http://ndltd.ncl.edu.tw/handle/52976067969880172238

碩士 === 國立交通大學 === 電子研究所 === 100 === In recent years, the enhancement of packing density through device scaling-down became slower because the scaling down of devices have met numerous bottlenecks in practical fabrication process. Since Moore’s law could not be satisfied by device scaling-down, the concept of three dimensional integrated circuits (3D-ICs) has been introduced. On account of the advantages of heterogeneous integration and chip stacking, 3D-ICs have been regarded as one of the options to achieve the trend of Moore’s law. Among the technologies of 3D-ICs, through silicon vias (TSV) played a crucial role in the connections between each chips. Nowadays, TSVs were usually filled with copper by conventional electroplating because of the low resistivity of copper. However, since the rapid increasing of TSV aspect ratios, the difficulty of TSV copper filling has also been increased. To realize the TSVs with high aspect ratio and low electrical resistivity, new materials must be taken into consideration. Therefore, carbon nanotubes (CNTs) have been thought as one of the promising materials in TSVs. In this thesis, co-deposited metals have been used to control the density of catalyst nanoparticles, and achieve high density of CNT bundles. The resistance of CNT-based TSVs is expected to be reduced with the dense CNT bundles. Our purpose is to establish CNT-first approach for CNT-based TSVs with high aspect ratio and low electrical resistivity for 3D-IC applications. By setting the ratios of co-deposited Co-Ti metals to be 1:3, 1:1, 3:2 and 3:1, the distribution of catalyst nanoparticles could be controlled. Co-deposited catalyst nanoparticles with smallest size and highest density would be regarded as the best solution to grow CNTs. Ethylene (C2H4) and hydrogen (H2) were used as the growth gases for growing CNTs. The ratio of ethylene and hydrogen was also optimized to grow aligned CNTs with the height of 50 ~ 70 um for the application of TSVs. By controlling the ratio of co-deposited Co-Ti metals to be 1:1, the wall density of CNTs exceeding 1012 cm-2 could be obtained. Then, CNT bundles with the height higher than 50 um could be achieved by using the optimized flow rates of 100 sccm ethylene and 100 sccm hydrogen. The CNTs bundles with high wall density and the height of 50 ~ 70 um could be achieved for CNT-based TSVs. Deformation of CNT bundles would be occurred by directly depositing SU-8 dielectric layer on CNT bundles. By covering the CNT bundles with an oxide film before SU-8 dielectric layer spin coating, SU-8 dielectric layer could be blocked and the deformation of CNT bundles could be avoided. As the thickness of TEOS-oxide was increased to 2 um, CNT bundles would be tor into pieces during polish process and the TSV structures would be broken. Therefore, the TEOS-oxide with 1 um in thickness was used. SU-8 dielectric layer would infiltrate into CNT bundles as a supporting layer and the deformation of CNT bundles during polishing process could be avoided. In this thesis, CNT-first approach of CNT-based TSVs has been achieved. The resistivity of our CNT bundles could be obtained to be 0.43 Ω‧cm by measuring TSVs with different via heights. Schottky contact has been found between silicon substrate and the bottom metal layer Ti under CNT bundles. To reduce the influence of Schotkky contact , CNT-based TSVs have been heated to 200 ℃. Ohmic behaviors have been found and the resistivity could be reduced to 0.34 Ω‧cm at 200 ℃. It means if the Schottky contact could be removed from our structure, the CNT-based TSVs with excellent characteristics and simple fabrication process produced by utilizing CNT-first approach could be obtained, and could be applied in the 3D-ICs.