On Constructing Low Power and Robust Clock Tree
碩士 === 國立交通大學 === 電子研究所 === 100 === Timing check is a critical stage in clock tree synthesis (CTS). Since no previous work has addressed on accurate timing model and most related works perform skew optimization by embedding SPICE simulation process into CTS flow, we should have more efficient timing...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/00447693781120674184 |