| Summary: | 碩士 === 國立交通大學 === 電信工程研究所 === 100 === High-κ/metal gate technology has been recently recognized as the key to sub-45-nanometer transistor fabrication because of the improvement of device performance and reduction of intrinsic parameter fluctuation. However, the use of high-κ/metal gate device
introduced new sources of variation. The generated traps at the interface of high-κ/silicon, a new random fluctuation source, is associated with the oxygen vacancies in the interface of HfO2/silicon caused by its interaction with the overlaying high-k/metal stack.
It will degrade the of device performance and induce threshold voltage (Vth) variation. In this thesis, we study the DC/AC and transfer characteristic fluctuation in 16-nm-gate high-κ/metal gate devices and circuit induced by random interface traps at high-κ/silicon interface. Totally random generated devices with two-dimensional interface traps at HfO2/silicon are incorporated into three-dimensional quantum-mechanically corrected device simulation. Effects of random ITs number and position on device characteristic
fluctuations inclduing threshold voltage, on-/off-state current, maximum transconductance, output resistance of transistor, drain-induced barrier lowering, gate capacitance, and cutoff frequency are examined. Not only interface traps, we also investigate the effects
of combined random dopants and interface traps on electrical characteristics of 16-nm high-κ/metal gate devices. Two-dimensional ITs at HfO2/silicon film interface and three-dimensional random dopants inside the silicon channel are simultaneously incorporated into an experimentally validated three-dimensional device simulation to quantify the random-dopants-and-interface-traps-fluctuated characteristics.
Additionally, one of the main issues for high-κ/metal gate devices is the charge trapping characteristics under dynamic operation. It remains an important reliability issue which causes the Vth shift and drive current degradation. Therefore, we examine the effects of trapping/de-trapping on Vth reliability in high-κ/metal gate devices by an experimentally validated device simulation. Totally random generated devices with two-dimensional bulk traps in HfO2 layer are incorporated into quantum-mechanically corrected device simulation. We investigate the influences of frequency and duty cycle
dependences on the device Vth shift. The Vth shift increases as the frequency decreases or duty cycle increases. On the other hand, effects of random bulk trap’s number and position on device Vth shift due to trapping and de-trapping is also studies.
In summary, we have studied the influences of the 2D interface traps and combined 2D interface traps and 3D random dopants induced characteristics fluctuations on 16-nm-gate devices and digital circuit. Under dynamic operation, the effects of the random
2D bulk traps which is positioned in the HfO2 region on the 16-nm-gate MOSFETs with TiN/HfO2 have also been discussed and simulated. We believe the results of this study is useful for sub-22-nm technology node transistor.
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