Design and Implementation of an Energy-Efficient Programmable Vertex Processor with Ray-Tracing Acceleration

• Main Authors: Liu, Ruei-Jyun, 劉睿峻
• Other Authors: Van, Lan-Da
• Format: Others
• Language: en_US
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/79716181762820169949

碩士 === 國立交通大學 === 多媒體工程研究所 === 100 === In this work, an energy-efficient programmable vertex processor with ray-tracing acceleration is proposed. The proposed vertex processor architecture has four features: 1) four-issue floating-point VLIW datapath; 2) multilevel pre-TnL and post-TnL vertex cache functions; 3) Whitted-style ray-tracing supported; 4) hardware sharing between the intersection and back-face culling processing. From the chip implementation result in TSMC 90nm CMOS process technology, the operating frequency can be up to 100MHz. The post-layout simulation indicates that the vertex fill rate with and without lighting can achieve 4.5Mvertices/s and 100Mvertices/s, respectively. The resulting power efficiency is 268.33Kvertices/mJ.