Overlay Error Control of Lithography Process

• Main Authors: Cha, Meng-Hsun, 詹孟勳
• Other Authors: Cheng, Stone
• Format: Others
• Language: zh-TW
• Published: 2011
• Online Access: http://ndltd.ncl.edu.tw/handle/32957879172160993341

碩士 === 國立交通大學 === 平面顯示技術碩士學位學程 === 100 === In semiconductor manufacturing process, the overlay error is an important issue in photolithography process control. This overlay error is generated by Box-in-Box structure variation in measurement process. For wafer manufacture, pre-layer of the chips is located on the outside area of big box frame, the present-layer of the chips is located in the inside area of small box frame. Due to the measurement process change, these two box frame's relative positions are different, and cause the overlay error from the present-layer to pre-layer. The improvement of overlay error is controlled by 10 parameters. The purpose of this thesis is for global alignment step of wafer exposure flow in lithography process. To reduce overlay error, a suitable alignment mark is chosen from the actual operation experiments. Different alignment marks are evaluated by completing the mask layout and analyzing the data of actual samples run to discover most suitable alignment mark at this layer. After discovering a most suitable mark, operation recipe is changed and verified. Comparing the overlay measuring residuals, X Mean + 3-sigma, Y Mean + 3-sigma, and the overlay control 10 parameters, the experiment confirmed that the alignment mark affects overlay error measured data, and influences the ability of overlay error control. Another experiment is overlay error measurement mark estimation. The lithography process and etching process is to discover a smallest measurement mark. For most suitable measuring mark obtained by experiment, the operation recipe is revised.