A Dual-Looped Clock and Data Recovery Circuit with the Use of Data Delay Window
碩士 === 國立中央大學 === 電機工程研究所 === 100 === In recent year, owing to the development of network and processor, the requirement of the high-speed data transmission has become the main motivation of transmission system. The conventional parallel bus shows the serious restriction while operating in the gigah...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/45328191405507126337 |