| Summary: | 碩士 === 國立中央大學 === 電機工程研究所 === 100 === Due to the sensitivity of analog components, the evolution of process technologies, and the size shrink of components, post-layout electrical effects increasingly impact the circuit performance. In order to reduce the electrical effects, the layouts of most analog designs are done by manual. Although layouts of partial designs can be done by EDA tools with experience of engineers, the development of analog design automation cannot be easily broken through due to a large number of layout constraints.
Although there are many literatures on analog placement, the number of researches on analog placement considering routing is few. In the placement process, although we can use the topology constraints to reduce the mismatch, the unexpected electrical effects will be produced by the routing paths. In order to reduce the electrical effects produced by the routing paths, routing paths must avoid the analog devices, implying that enough routing spaces are needed to be preserved in the placement stage.
This work presents an analog placement flow to handle the symmetry constraints, and to preserve enough routing spaces between devices. The flow is based on the deferred decision making (DDM) technique. Using DDM technique cannot only generate non-stochastic solutions, but also provide multiple and flexible solutions for engineers.
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