Design of High Performance Low Power Delay-Locked Loops
碩士 === 國立東華大學 === 電機工程學系 === 100 === In recent years, because of the advances in integrated circuit process technology, a size of device is reduced continuously. A high speed clock signal for more and more complicated and high-speed systems are needed. Delay-locked loop (DLL) with easy to design...
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| Format: | Others |
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2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/k633es |