Simulation of a P-Type Junctionless Double-Gated Poly-Si Nanowire Transistor
碩士 === 國立東華大學 === 電機工程學系 === 100 === As the scaling of devices , it was a problem to work a steeply PN junction for semiconductor technology these days. We considered a non–junction nanowire transistor whose source, drain and channel were the same doping type. In this way, we could make a transistor...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Published: |
2012
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/zryz3y |