| Summary: | 碩士 === 國立東華大學 === 電機工程學系 === 100 === As the scaling of devices , it was a problem to work a steeply PN junction for semiconductor technology these days. We considered a non–junction nanowire transistor whose source, drain and channel were the same doping type. In this way, we could make a transistor without a steeply PN junction and decrease the difficulty of the processing. The processing parameters were provided by Mr. Horng-Chih Lin’s laboratory in National Chiao Tung University. And we used the commercial semiconductor device simulator, Sentaurus, to simulate the electrical characteristics. In this study, we had three gate configurations：single gate 1（SG1）、single gate 2（SG2） and double gate（DG）. Discovering the effectives of three configurations. The simulation results show that the on current（Ion）and subthreshold swing（S.S.）of DG is better than that of SG1 and SG2. The on current（Ioff） is increased of the device with the P–type channel rather than the intrinsic. It shows that P–type junction–free nanowire transistor effectively increases the Ion. In addition, the performance of DG without top gate is more better than SG1 and SG2. We also change the position of contacts about source and drain. We simulate three contact configurations. Accroding to the results, the device with four contacts on both sides of the source and drain increase a little drain current.
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