A High Performance Register Allocator for Vector Architectures with a Unified Register-Set
碩士 === 國立中山大學 === 資訊工程學系研究所 === 100 === This thesis describes a compiler optimization targeted for machines with unified, vector-based register sets. This optimization combines register allocation and instruction scheduling. It examines places where the code performs computations on scalar varia...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/31411393752388548989 |