Thermal stress analysis for through silicon via structure
碩士 === 國立清華大學 === 動力機械工程學系 === 100 === Recently 3D chip integration is an emerging technology. It can achieve high package density and integration of heterogeneous chip. Through silicon via provides vertical interconnections between stacking dies in 3D chip integration. However, there are still some...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/42341911615594403519 |