Thermal stress analysis for through silicon via structure

• Main Authors: Kuo, Chi-Wei, 郭騏緯
• Other Authors: Tsai, Hung-Yin
• Format: Others
• Language: zh-TW
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/42341911615594403519

碩士 === 國立清華大學 === 動力機械工程學系 === 100 === Recently 3D chip integration is an emerging technology. It can achieve high package density and integration of heterogeneous chip. Through silicon via provides vertical interconnections between stacking dies in 3D chip integration. However, there are still some challenges for this technology such as heat dissipation of 3D chip and large differences of coefficient of thermal expansion (CTE) in TSV structure. Due to the large thermal mismatch, the thermal stress at the interface of materials may result in the reliability problem of chip. In this study, the thermal-mechanical stress distribution of a three dimensional TSV array model and bonding pad of TSV structure under the condition of accelerated thermal cycling loading is investigated by finite element analysis software-ANSYS®. Furthermore, the effect of geometry parameter of TSV to thermal stress is studied and analyzed by factorial designs and sensitivity analysis. According to the simulation result, the nickel at the TSV structure annular edges is stretched at 125 ﾟC and contracted at -40 ﾟC by the thermo expansion of other material, so the maximum thermal stress occurs at the nickel. Besides, the stress also occurs at the interface of silicon and silicon dioxide which may result in failure or delamination of TSV pads. In addition to, the parametric sensitivity analysis result shows that reducing the pad diameter is the most effective way to lower the thermal stress. Reduce the diameter ratio and increase the pitch between TSV can also lower the thermal stress. With these results, this study helps to obtain a clear thermal stress distribution of TSV array and possible failure regions in the TSV structure.