Yield-enhanced Analog and RF Layout Optimization
碩士 === 國立清華大學 === 資訊工程學系 === 100 === As technological process continue to evolve in recent years, from 180nm, 90nm, 65nm, 40nm until 28nm, while the dimension of device keeps on shrinking. However, process variations have a large impact on circuit performance by decreasing the rate of the prod...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/82764796389505293688 |