An Instruction-Oriented Approach for Efficient Timed Out-of-Order Processor Simulation
碩士 === 國立清華大學 === 資訊工程學系 === 100 === In this paper we propose a highly efficient timed model for pipelined out-of-order processors based on resource usage analysis. Existing timed processor models either are limited to simple processor architectures or are inefficient for system simulation purpose a...
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| Format: | Others |
| Language: | zh-TW |
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2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/02533818764992543211 |