A Time-to-Digital Converter Using Vernier Delay Line with Time Amplification Technique
碩士 === 國立清華大學 === 工程與系統科學系 === 100 === This paper describes the design of using time amplification in time-to-digital converter (TDC) with two level vernier delay line (VDL), which is used to solve the limitations of chip area, power consumption, and device mismatching of VDL in 10 picoseconds or le...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/43129891562371672018 |