Smart Fault-Tolerant Path: A New Path Selection Strategy for Network-on-Chip
碩士 === 國立臺灣大學 === 電子工程學研究所 === 100 === Networks-on-Chip (NoC) have been proposed to solve increasing scale and complexity of designs in nano-scale VLSI designs. Efficient and deadlock-free routing is critical to the performance of Networks-on-Chip. In this thesis, we proposed an approach, Smart Fa...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/84554625161410191842 |