Layout Decomposition for Triple Patterning Lithography

• Main Authors: Wei-Yu Chen, 陳威宇
• Other Authors: 張耀文
• Format: Others
• Language: en_US
• Published: 2011
• Online Access: http://ndltd.ncl.edu.tw/handle/12296490883899231236

碩士 === 國立臺灣大學 === 電子工程學研究所 === 100 === Double patterning lithography (DPL) has been widely recognized as one of the most promising solutions for the sub-22nm technology node to enhance pattern printability. However, much of the literature from industry states that, for the 15nm technology node and beyond, triple patterning lithography (TPL) will be required for the gate, contact, and metal one layers, which are too complex and dense to be split into two masks. Unfortunately, until now, there is very little research focusing on the layout decomposition for TPL. Recent work presented by Yu et al. proposed the first systematic study on the layout decomposition for TPL. However, we observe that their proposed algorithm may miss several possible stitch locations and result in some conflicts that can be resolved by inserting stitches. In this thesis, we first point out two main differences between DPL and TPL layout decompositions. Based on these two differences, we first present a graph division method consisting of four reduction techniques to reduce the problem size without degrading overall solution quality. Next, we propose a stitch-aware mask assignment algorithm, which is based on a heuristic that finds a mask assignment such that the conflicts among the features in the same mask are more likely to be resolved by inserting stitches. Experimental results show that our graph division method can significantly reduce the problem size by an average of 93%, and that the proposed stitch-aware mask assignment algorithm can achieve around 38% reduction of conflicts compared to a basic mask assignment method.