Analytical Placement for FPGAs
碩士 === 國立臺灣大學 === 電子工程學研究所 === 100 === Placing a technology-mapped netlist of logic blocks onto a 2D array of pre-fabricated con gurable logic blocks (CLB) on a eld programmable gate array (FPGA) chip is a classical problem. However, the increasing design complexity of modern circuits has reshaped...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/77095654871061907731 |