Simulation Study of Vertical Pillar Transistor and Ge Gate-All- Around FET
碩士 === 國立臺灣大學 === 電子工程學研究所 === 100 === For next generation highly-integrated DRAMs, 4F2 cell array structure composed of a capacitor stacked vertically on a cell transistor is required. Vertical pillar transistor (VPT) is regarded as the most promising candidate for cell transistor in the 4F2 cell a...
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| Format: | Others |
| Language: | en_US |
| Published: |
2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/67457753346432652617 |