Practical Standard Cell Library Optimizer for Improving Rate of Redundant Via Insertion
碩士 === 國立臺灣科技大學 === 電子工程系 === 100 === Via failures are an ongoing challenge in nanometer-scale semiconductor manufacturing processes. Adding redundant vias is the standard method for increasing yield and reliability. Cell-based design approaches are extensively adopted for physical implementation. S...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2012
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/98434889340520872768 |