Design for Testability ( DFT ) of Cryptographic SoC with IEEE Std. 1500
碩士 === 國立高雄大學 === 電機工程學系碩士班 === 100 === This thesis proposes several test reuse mechanisms in a Cryptographic SoC to let the hardware modules (IP) be easier to be tested. The IEEE Std. 1500 uses boundary scan structure to test the IP. It need to spend more time when using IEEE Std. 1500 serial testi...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/64157843133237111440 |