A 10-bit 100M Sa/s Current-Steering Digital-to-Analog Converter
碩士 === 樹德科技大學 === 電腦與通訊系碩士班 === 100 === In this thesis, a 10-bit 100MSa/s current-steering digital-to-analog converter is implemented using TSMC 0.35um 2P4M mixed signal CMOS technology. The DAC adopts the segmented architecture which comprises a segment of 6-bit into 63 equally weighted current so...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/21579620518337268165 |