| Summary: | 碩士 === 國立臺北科技大學 === 電機工程系研究所 === 100 === The methods to represent a floorplan of VLSI can be classified as slicing and non-slicing. The non-slicing method can express slicing structure as well as non-slicing structure while the slicing method can express slicing structure only. However, there are reasons that make the slicing method survive: (1) Slicing method is simple in terms of implementation; (2) A floorplan designed with slicing method should be maintained accordingly; (3) After compression, a slicing flooplan becomes a non-slicing floorplan.
Instead of ‘H’ and ‘V’, we use ‘O’ in our relaxed Polish expression to relax the constrained on the orientation of cut. In addition, we propose a greedy merging algorithm to work with the proposed relaxed Polish expression. Further, we use GPU to perform parallel computation. Finally, we use constrained longest common subsequence to convert a slicing structure to a non-slicing structure.
GSRC and MCNC Benchmarks are used as test circuits in our experiments. The experimental results show that our approach significantly accelerated the speed of calculation, and the proposed parallel simulation annealing algorithm make the results better, while the constrained longest common subsequence can efficiently convert a slicing structure to a non-slicing structure.
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