Chip Design of Low Latency Parallel Turbo Decoder with Synchronous Output
碩士 === 國立臺北科技大學 === 電腦與通訊研究所 === 100 === Turbo code has excellent decoding performance which is one of close to the Shannon-limit error correction codes. In order to achieve requirement of the modern communication, turbo codes employ multiple SISO decoders by intuition. However, parallel decoders wi...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2012
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/5y8xbk |