Chip Design of Low Latency Parallel Turbo Decoder with Synchronous Output
碩士 === 國立臺北科技大學 === 電腦與通訊研究所 === 100 === Turbo code has excellent decoding performance which is one of close to the Shannon-limit error correction codes. In order to achieve requirement of the modern communication, turbo codes employ multiple SISO decoders by intuition. However, parallel decoders wi...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2012
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/5y8xbk |
| Summary: | 碩士 === 國立臺北科技大學 === 電腦與通訊研究所 === 100 === Turbo code has excellent decoding performance which is one of close to the Shannon-limit error correction codes. In order to achieve requirement of the modern communication, turbo codes employ multiple SISO decoders by intuition. However, parallel decoders will degrade the correcting performance dramatically as a result of shortening the interleaver length. Thus in this thesis, we proposed a low latency parallel decoding with synchronous output turbo decoder. It can improve both latency and error correction ability in comparison with general parallel turbo decoders. Simulation results show that the error correction ability is close to the traditional turbo decoder and the whole decoding latency can be reduced 51.3%~58.6% with different block length, also can achieve 11.7Mbps throughput with 8 iterations at 100MHz working frequency. For verifying this work, we have used FPGA to emulate the hardware architecture and designed this chip with TSMC 0.18μm CMOS process. The gate count is 151396. The chip size including I/O pad is 3.42mm2.
|
|---|