THE CONTROLLER IP DESIGN OF MULTIPLE DATA ACCESS PORT FOR DDR SDRAM
碩士 === 大同大學 === 電機工程學系(所) === 100 === At first we introduce the electrical characteristic of the random access memory, including static random access memory（SRAM）and double data rate dynamic random access memory（DDR SDRAM）,and consider to construct a multiple data access port memory controller to DD...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2012
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/12408988075884289355 |
| Summary: | 碩士 === 大同大學 === 電機工程學系(所) === 100 === At first we introduce the electrical characteristic of the random access memory, including static random access memory（SRAM）and double data rate dynamic random access memory（DDR SDRAM）,and consider to construct a multiple data access port memory controller to DDR SDRAM devices.
In order to implement the multiple data access port function to a single DDR SDRAM device, we use time division multiplexing technique and use a central arbiter to control the resource using scheduling. We also use a flexible weightighting parameter and priority code for those data access ports toachieve good flexible bandwidth share and priority setting when this controller IP is integrated to other circuit.
We use Verilog 2001 to write the RTL source code and verify the circuit function by simulation tool Modelsim. Finally, we implement the controller by Altera Cyclone IV Family FPGA and use Altera FPGA design tool Quartus II to generate the compilation Report for this design.
|
|---|