DESIGN OF THE PHASE-LOCKED LOOP FREQUENCY SYNTHESIZER FOR 802.11a
碩士 === 大同大學 === 電機工程學系(所) === 100 === In this thesis, we refer to the IEEE 802.11a standard and design a 5.8GHz phase-locked loops frequency synthesizer fitting the specification. The phase-locked loops frequency synthesizer consists of a phase-frequency detector, charge pump, loop filter, LC-tank V...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/21729362255888179132 |