DESIGN OF ALL DIGITAL PHASE-LOCKED LOOP CIRCUITS
碩士 === 大同大學 === 電機工程學系(所) === 100 === In this thesis, we designed an all digital phase locked loop (ADPLL). Its structures included phase frequency detectors, time to digital converter, loop filter, digital controlled oscillators, buffer and divider. This thesis not only proposed a new modified time...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/24031698315028043856 |