| Summary: | 碩士 === 大同大學 === 電機工程學系(所) === 100 === In this thesis, we designed an all digital phase locked loop (ADPLL). Its structures included phase frequency detectors, time to digital converter, loop filter, digital controlled oscillators, buffer and divider. This thesis not only proposed a new modified time to digital converter which can transform all the impulse into a digital string signal but also modified the circuits of buffer which make all the circuits work well and without interfering of signal delay. Finally, we know that the ranges of locking frequency error are -0.68%~1.62%. The output frequency ranges are 152~581MHz. In this thesis, we use Xilinx Spartan3E XC3S1600E-5FG320, MODELSIM PE 10.1a and ISE 10.1 to check new modified time to digital converter, BUF and all other circuits.
|
|---|
