Programmable Integral / Fractional Clock Synthesizer based on Delay-Locked Loop
碩士 === 國立雲林科技大學 === 電機工程系碩士班 === 100 === With the advancement in the semiconductor process technologies, the operating speed in the System-on-a-Chip is raised up to gigahertz. In this manner, the jitter performance of the synthesized clocks becomes more important. Most of the clock synthesizers adop...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/93736241207298666966 |