A Fast-Locking Duty Cycle Corrector With Deskew Capability
碩士 === 國立雲林科技大學 === 電機工程系碩士班 === 100 === In this paper, a fast-locking all-digital duty cycle corrector has simple architecture is proposed. It is using the feature of two Half Delay Line (HDL) which is a delay of HDL is equal to a half of input clock period for correcting the output clock duty cycl...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2013
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| Online Access: | http://ndltd.ncl.edu.tw/handle/26144604445639018225 |